1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to a method and apparatus for protecting integrated circuits from electrical overstress and electrostatic discharge.
2. Discussion of the Related Art
Electrical overstress (EOS) of an integrated circuit generally results from an external source discharging large transient voltages typically over a short period of Lime onto a terminal or pin of the integrated circuit. EOS events include very fast transients such as electrostatic discharge (ESD), and slower transients produced by powerline glitches or dropouts.
Electrostatic discharge or ESD is a well-known cause of operation failure of integrated circuits. The build-up of electrostatic charge on personnel and equipment during the manufacture and use of integrated circuits may assume potentials as high is 30,000 volts with respect to an ESD reference point. The built-up charge may be dischargec through an integrated circuit when either the personnel or the equipment comes in contact with the integrated circuit. The electrostatic discharge may occur during manufacturing or testing when the integrated circuit is non-operating, or it may occur when the integrated circuit is installed in a device and is operating. Integrated circuits are particularly susceptible to ESD damage during handling in a manufacturing, testing or printed circuit board assembly environment.
An electrostatic discharge through an integrated circuit can permanently damage the integrated circuit through several failure mechanisms including the dielectric breakdown of oxides and other thin layers, the melting of conductive material such as polysilicon or aluminum, and the melting of semiconductor material such as silicon, resulting in excessive leakage currents and open or short circuits in the integrated circuit.
Several test procedures exist for testing integrated circuits and determining sensitivity threshold levels of integrated circuits to electrostatic discharge. These test procedures include: American National Standards Institute (ANSI)/ESD Association Standard S5.1 Human Body Model (HBM) for simulating an ESD event generated by the human body; ANSI/ESD Association Standard S5.2 Machine Model (MM) for simulating an ESD event generated by a charged metal object such as a machine; and ESD Association Draft Standard DS5.3 Socketed Charge Device Model (SCDM) for simulating electrostatic discharges to integrated circuits during manufacture and test due to the use of automated equipment. Because of the pervasive use of automated equipment in testing, handling and manufacturing of integrated circuits, SCDM discharges are the predominant cause of manufacturing-related ESD failures. Devices which exhibit low thresholds to damage from an electrostatic discharge may be subject to special handling procedures and may also incorporate EOS/ESD protection devices.
The special handling procedures may include the use of anti-static materials on manufacturing floors, bench tops, and other surfaces used during the manufacture and testing of integrated circuits. Additionally, operators handling sensitive integrated circuits may be required to wear wrist or ankle straps that are resistively connected to a voltage potential such as ground, to prevent electrostatic charge build-up on their bodies.
Integrated circuits containing metal oxide semiconductor (MOS) transistors are particularly sensitive to electrostatic discharge at their input, output, and supply pins. Several approaches to FOS/ESD protection circuits have been developed to protect MOS transistors from EOS/ESD events at their input, output, and supply pins. These circuits often consist of large parallel protection circuits, external to the devices to be protected, which comprise diodes, thick oxide MOS devices, and silicon controlled rectifiers (SCRs). These large parallel protection circuits often also include a series resistor. U.S. Pat. No. 4,829,350, titled "Electrostatic Discharge Integrated Circuit Protection", and issued to Bernard D. Miller, discloses in ESD protection circuit for the input pins of CMOS integrated circuits that includes a series resistor and parallel clamping diodes. This patent also discloses the use of clamping diodes disposed in parallel with the output pins to provide ESD protection for the output pins. U.S. Pat. No. 4,896,243, titled "Efficient ESD Input Protection Scheme", and issued to Amitava Chaterjee, et al., similarly discloses an ESD protection circuit for the input of an integrated circuit that employs a series resistor and a parallel clamping diode.
There are several known disadvantages to using the ESD protection circuits of the prior art. Parallel clamping diodes require a relatively large area, exhibit undesirable parasitic capacitance and leakage current, and may have undesirably high "on" resistance. Also, such large diode clamps require a low impedance return path as described in U.S. Pat. No. 4,839,768, titled "Protection of Integrated Circuits From Electrostatic Discharges", and issued to Viscenzo Daniele, et al. Without a low impedance return path, the effectiveness of these large diode clamps is greatly reduced. Additionally, large clamping devices may not be standard devices that can be included on integrated circuits without special processing steps. Furthermore, non-standard devices used to provide ESD protection in some cases are not manufactured to the same quality standards as the integrated circuits to be protected and, as a result, may have greater voltage breakdown tolerances, leading to less predictable ESD protection behavior. The use of series resistors in some applications also is undesirable, particularly on output pins, since series resistance reduces the drive capability of output drivers.
Other prior art FOS/ESD protection circuits utilize an NMOS protection device that is off during normal circuit operation in the absence of an EOS or ESD event. During an EOS/ESD event, the off NMOS device exhibits a reverse breakdown that triggers parasitic bipolar transistor action that discharges the EOS/ESD event through a number of discharge channels or "fingers" that are formed in the device. These prior art NMOS protection devices also lave several associated problems. The parasitic parameters of NMOS devices typically are not well controlled, and accordingly, the voltage at which an NMOS device will brealk down and the current at which it will exhibit bipolar snap back to a lower voltage are not well controlled. Also, the large parasitic parameters associated with these devices preclude their use in some applications. Further, individual fingers within an NMOS device will turn or at different times in response to an EOS/ESD event. This results in a non-uniform distribution of discharge current through the device and causes localized "hot" spots which may damage the NMOS device. To compensate for the above described limitations, the prior art NMOS protection devices typically are relatively large, to allow for parallel discharge of an EOS/FSD event through a plurality of fingers to reduce localized heating.